Before convergence early stopping criterion for inner LDPC code in DVB standards

International audienceThis letter presents a "before convergence" early stopping criterion for the LDPC decoder defined in the second generation of DVB standards. The idea is to stop the decoding process once the estimated number of remaining errors is below the maximum capacity correction of the outer BCH decoder used in the DVB-S2, T2 and C2 standards. Simulations show that the average number of iterations is reduced by up to 26% compared with classical early stopping criterion up to a frame error rate of 10^-6

Muller C-element based Decoder (MCD): A Decoder Against Transient Faults

This work extends the analysis and application of a digital error correction method called Muller C-element Decoding (MCD), which has been proposed for fault masking in logic circuits comprised of unreliable elements. The proposed technique employs cascaded Muller C-elements and XOR gates to achieve efficient error-correction in the presence of internal upsets. The error-correction analysis of MCD architecture and the investigation of C-element’s robustness are first introduced. We demonstrate that the MCD is able to produce error-correction benefit in a high error-rate of internal faults. Significantly, for a (3,6) short-length LDPC code, when the decoding process is internally error-free the MCD achieves also a gain in terms of decoding performance by comparison to the well-known Gallager Bit-Flipping method. We further consider application of MCD to a general-purpose fault-tolerant model, coded Dual Modular Redundancy (cDMR), which offers low-redundancy error-resilience for contemporary logic systems as well as future nanoeletronic architectures

Noise-aided gradient descent bit-flipping decoders approaching maximum likelihood decoding

International audienceIn the recent literature, the study of iterative LDPC decoders implemented on faulty-hardware has led to the counter-intuitive conclusion that noisy decoders could perform better than their noiseless version. This peculiar behavior has been observed in the finite codeword length regime, where the noise perturbating the decoder dynamics help to escape the attraction of fixed points such as trapping sets. In this paper, we will study two recently introduced LDPC decoders derived from noisy versions of the gradient descent bit-flipping decoder (GDBF). Although the GDBF is known to be a simple decoder with limited error correction capability compared to more powerful soft-decision decoders, it has been shown that the introduction of a random perturbation in the decoder could greatly improve the performance results, approaching and even surpassing belief propagation or min-sum based decoders. For both decoders, we evaluate the probability of escaping from a Trapping set, and relate this probability to the parameters of the injected noise distribution, using a Markovian model of the decoder transitions in the state space of errors localized on isolated trapping sets. In a second part of the paper, we present a modified scheduling of our algorithms for the binary symmetric channel, which allows to approach maximum likelihood decoding (MLD) at the cost of a very large number of iterations

HISD : un nouveau décodeur MIMO utilisant une approche géométrique pour des transmissions MAQ

Dans de nombreux systèmes de communication, l'opération de décodage se résume à résoudre un problème d'optimisation d'un système combinatoire de la forme y = Hx+b. Dans le cas général, son décodage au sens du maximum de vraisemblance (ML) est un problème connu de type « NP-Complet ». Dans cet article, afin de résoudre ce problème, un nouvel algorithme sous optimal appelé HISD (Hyperplane Intersection and Selection Detector) est proposé. Cet algorithme repose sur une approche géométrique. Comparé aux algorithmes existants, le HISD possède trois caractéristiques très attrayantes pour une implantation dans des systèmes réels. La première concerne ses performances en terme de TEB qui sont proches de celles de l'optimum (ML). Sa complexité en terme de calcul est faible et sa structure est intrinsèquement parallèle ce qui rend d'autant plus aisée son implantation matérielle. Dans cet article, l'algorithme HISD est utilisé pour résoudre de manière efficace le problème du décodage des systèmes de transmissions MIMO (Multiple Input Multiple Output)

A new Architecture for High Speed, Low Latency NB-LDPC Check Node Processing

International audience—Non-binary low-density parity-check codes have superior communications performance compared to their binary counterparts. However, to be an option for future standards, efficient hardware architectures must be developed. State-of-the-art decoding algorithms lead to architectures suffering from low throughput and high latency. The check node function accounts for the largest part of the decoders overall complexity. In this paper a new hardware aware check node algorithm and its architecture is proposed. It has state-of-the-art communications performance while reducing the decoding complexity. The presented architecture has a 14 times higher area efficiency, increases the energy efficiency by factor 2.5 and reduces the latency by factor of 3.5 compared to a state-of-the-art architecture

The Physicist's Guide to the Orchestra

An experimental study of strings, woodwinds (organ pipe, flute, clarinet, saxophone and recorder), and the voice was undertaken to illustrate the basic principles of sound production in music instruments. The setup used is simple and consists of common laboratory equipment. Although the canonical examples (standing wave on a string, in an open and closed pipe) are easily reproduced, they fail to explain the majority of the measurements. The reasons for these deviations are outlined and discussed.Comment: 11 pages, 10 figures (jpg files). Submitted to European Journal of Physic

Les turbo-codes à roulettes

é - Le problème majeur dans l'implémentation matérielle d'un turbo-décodeur réside dans le manque de parallélisme des algorithmes de décodage MAP. Cet article propose un nouveau procédé de turbo-codage basé sur deux idées: le codage de chaque dimension par P codes convolutifs récursifs circulaires indépendants et des contraintes sur la structure de l'entrelaceur qui permet de décoder en parallèle les P codes convolutifs dans chaque dimension. La construction des codes constituants et de l'entrelaceur est décrite et analysée. Un haut degré de parallélisme est obtenu avec des performances équivalentes ou meilleures que les meilleurs turbo-codes connus. L'architecture parallèle du décodeur permet de réduire la complexité du turbo-décodeur pour des applications à très hauts débits

Improving Network-on-Chip-based Turbo Decoder Architectures

In this work novel results concerning Networkon- Chip-based turbo decoder architectures are presented. Stemming from previous publications, this work concentrates first on improving the throughput by exploiting adaptive-bandwidth-reduction techniques. This technique shows in the best case an improvement of more than 60 Mb/s. Moreover, it is known that double-binary turbo decoders require higher area than binary ones. This characteristic has the negative effect of increasing the data width of the network nodes. Thus, the second contribution of this work is to reduce the network complexity to support doublebinary codes, by exploiting bit-level and pseudo-floatingpoint representation of the extrinsic information. These two techniques allow for an area reduction of up to more than the 40 % with a performance degradation of about 0.2 d